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INIC-1605 initio corporation 1 INIC-1605 usb to sata bridge specification version 1.01 august 14, 2006 initio corporation
INIC-1605 initio corporation 2 change history: 8-14-06 ? minor feature edits 8-4-06 - release
INIC-1605 initio corporation 3 table of contents h 1. introduction:............................................................................................................... ................ h 6 h 1.1 feature summary ......................................................................................................... .......... h 6 h 1.2 firmaware/software support................................................................................................. h 7 h 1.3 devices support............................................................................................................ ......... h 7 h 2. INIC-1605 block diagram ..................................................................................................... ..... h 8 h 3. pin-out diagram............................................................................................................. ........... h 9 h 4. pin signal description: (64-pin package) ................................................................................ h 10 h 4.1 usb interface (analog pins except vbus) ........................................................................ h 10 h 4.2 sata interface (analog pins) ............................................................................................ h 10 h 4.3 system interface ........................................................................................................... ....... h 10 h 4.4 miscellaneous interface.................................................................................................... ... h 10 h 4.5 serial flash interface ..................................................................................................... ...... h 11 h 4.6 mvram/gpio interface .................................................................................................... h 11 h 4.7 power regulator pins .................................................................................................. ....... h 12 h 4.8 power/gnd .................................................................................................................. ....... h 12 h 5. register address mapping:................................................................................................... ... h 12 h 5.1 general registers.......................................................................................................... ....... h 12 h 5.2 buffers .................................................................................................................... ............. h 13 h 5.3 usb control registers ...................................................................................................... .. h 13 h 5.4 sata control registers..................................................................................................... . h 13 h 5.5 data buffer................................................................................................................ ...... h 14 h 5.6 usb registers............................................................................................................. ......... h 14 h 5.7 data space mapping......................................................................................................... ... h 14 h 5.8 code space: internal sram: ................................................................................................. h 15 h 6. programming guide:.......................................................................................................... ...... h 15 h 6.1 usb direct access 8051?s code /data space (byte mode only)............................................. h 15 h 6.2 hardware program/download procedure (byte mode only)............................................... h 15 h 6.3 spi serial flash programming guide:................................................................................ h 16 h 7. register descriptions:...................................................................................................... ........ h 17 h 7.1 buffer reset register (0x40a3) ..................................................................................... h 17 h 7.2 test control register (0x40a6) ......................................................................................... h 17 h 7.2.1 led_spd register (0x40ac) .............................................................................................. h 17 h 7.2.2 miscen register (0x40ad) ................................................................................................. 18 h 7.3 miscctl register (0x40af): this 8 -registers is in lclk domain (37.5 mhz) ........................ h 18 h 7.4 softrst register (0x40b0).............................................................................................. ...... h 18 h 7.5 dma flush register (0x40b1)............................................................................................. h 18 h 7.6 usb channel set/clear register (0x40b2 set) (0x40b3 clear).......................................... h 18 h 7.7 dir/d2ben register (0x40b4) ............................................................................................. h 19 h 7.8 run register (0x40b5) ...................................................................................................... ... h 19 h 7.9 sata config register (0x40b6) ........................................................................................... h 19 h 7.10 sata reset register (0x40b7)............................................................................................ h 20 h 7.11 spi_ctrl/status register (0x40b d) (for spi-serial flash only) ....................................... h 20 h 7.12 spi_data register (0x40be) (for spi-serial flash only) ................................................. h 20
INIC-1605 initio corporation 4 h 7.13 spi_cmd register (0x40bf) (for spi-serial flash only)................................................ h 21 h 7.14 spi_adr[7:0] register (0x40dd) (for spi-serial flash only)........................................ h 21 h 7.15 spi_adr[15:8] regist er (0x40de) (for spi-serial flash only) ...................................... h 21 h 7.16 spi_adr[23:16] register (0x40d f) (for spi-serial flash only)..................................... h 21 h 7.17 usb_int_enable register (0x40f0).................................................................................. h 21 h 7.18 sata_int_enable register (0x40f2) ................................................................................. h 22 h 7.19 sata_busy_int register (0x40f3)..................................................................................... h 22 h 7.20 gpio_p_int_enable register (0x40f4).......................................................................... h 22 h 7.21 gpio_n_int_enable register (0x40f5) ......................................................................... h 22 h 7.22 buffer clear register (0x40f7)......................................................................................... h 22 h 7.23 gpio_enable register (0x40f8)....................................................................................... h 23 h 7.24 gpio_data register (0x40f9) .......................................................................................... h 23 h 7.25 gpio_output_enable register (0x40fa)......................................................................... h 23 h 7.26 usb clear register (0x40fb)........................................................................................... h 23 h 7.27 buffer address map ........................................................................................................ .... h 24 h 7.28 usb control ............................................................................................................... ......... h 24 h 8. sata channel registers ( 0x4800-0x483f): ............................................................. h 24 h 8.1 command parameter blocks (cpb) structure definition................................................... h 24 h 8.1.1. ata error shadow ........................................................................................................ ..... h 24 h 8.1.2. ata status shadow ....................................................................................................... ..... h 24 h 8.1.3. control flags ........................................................................................................... ............ h 25 h 8.1.4. reserved ............................................................................................................... .............. h 25 h 8.1.5. ata feature shadow...................................................................................................... .... h 25 h 8.1.6. ata extended feature shadow.......................................................................................... h 25 h 8.1.7. ata device/head shadow................................................................................................. h 25 h 8.1.8. ata sector count shadow................................................................................................. h 25 h 8.1.9. ata extended sector count shadow................................................................................. h 25 h 8.1.10. ata sector number shadow ........................................................................................... h 26 h 8.1.11. ata extended sector number shadow ........................................................................... h 26 h 8.1.12. ata cylinder low shadow ............................................................................................. h 26 h 8.1.13. ata extended cylinder low shadow ............................................................................. h 26 h 8.1.14. ata cylinder high shadow............................................................................................. h 26 h 8.1.15. ata extended cylinder high shadow............................................................................. h 26 h 8.1.16. ata command shadow ................................................................................................... h 26 h 8.1.17. ata control shadow..................................................................................................... ... h 26 h 8.2 sata phy low control register ( 4820h) ....................................................................... h 27 h 8.3 sata phy highcontro l register ( 4821h)........................................................................ h 27 h 8.4 sata phy low status register ( 4822h).......................................................................... h 27 h 8.5 sata phy high status register ( 4823h) ......................................................................... h 27 h 8.6 sata status register ( 4830h-4833h)................................................................................ h 28 h 8.7 sata error register ( 4834h-4837h) ................................................................................. h 28 h 8.8 sata control register ( 4838h-483bh)............................................................................. h 28 h 9. data buffer................................................................................................................. ......... h 28 h 10. usb registers:............................................................................................................. ............ h 28 h 10.1 device status(dev_status[7:0], 0x6020)............................................................................. h 28 h 10.2 function address(funct_adr[7:0], 0x6021)......................................................................... h 28
INIC-1605 initio corporation 5 h 10.3 test mode(test_mode[7:0], 0x6022) ................................................................................... h 28 h 10.4 end point tx data length low bytes (ep_txlength[7:0], 0x6025).................................. h 29 h 10.5 end point tx data length high bytes (ep_txlength[15:8], 0x6026) ............................... h 29 h 10.6 end point 0 status/control(ep0_st atus[7:0], 0x6030: set, 0x6031: clear) ......................... h 29 h 10.7 end point 0 status/control2(ep0_status2[7:0], 0x6032: set, 0x6033: clear, bulk-in)...... h 29 h 10.8 end point tx data length low bytes (ep0txlength[7:0], 0x6034).................................. h 30 h 10.9 setup packet (hdr0?hdr7[7:0], 0x6038?0x603f) ............................................................ h 30 h 10.10 end point 1 status/control(ep1_status[ 7:0], 0x6040: set, 0x6041: clear, bulk-in)........ h 30 h 10.11 end point 2 status/control(ep2_status[ 7:0], 0x6050: set, 0x6051 clear, bulk-out)..... h 30 h 10.12 usb_rxlength(usb_rxlength[7:0], 0x6052, bulk-out).................................................... h 30 h 10.13 end point 3 status/control(ep3_status[ 7:0], 0x6060: set, 0x6061: clear, intr-in) ..... h 31 h 10.14 end point tx data length low bytes (ep3txlength[7:0], 0x6062) ............................... h 31 h 10.15 total count0 (totalcnt[7:0], 0x6070 totalcnt0)............................................................... h 31 h 10.16 total count1 (totalcnt[15:8], 0x6071 totalcnt1)............................................................ h 31 h 10.17 total count2 (totalcnt[23:16], 0x6072 totalcnt2)........................................................... h 31 h 10.18 total count3 (totalcnt[31:24], 0x6073 totalcnt3).......................................................... h 31 h 10.19 load total count (load totalcnt, 0x6074) ....................................................................... h 31 h 10.20 global total count0 (gtotalcnt[7:0], 0x6080 gtotalcnt0)............................................ h 32 h 10.21 global total count1 (gtotalcnt[15:8], 0x6081 gtotalcnt1)........................................... h 32 h 10.22 global total count2 (gtotalcnt[23:16], 0x6082 gtotalcnt2)......................................... h 32 h 10.23 global total count3 (gtotalcnt[31:24], 0x6083 gtotalcnt3)......................................... h 32 h 11. electrical information: ................................................................................................... ......... h 32 h 11.1 absolute maximum ratings................................................................................................ h 32 h 11.2 recommended operating conditions.................................................................................. h 32 h 11.3 general dc characteristics ................................................................................................ . h 32 h 11.4 dc electrical characteristics for 3.3v operation ............................................................... 33 12. packaging specification???????????????????????????34
INIC-1605 initio corporation 6 1. introduction: the INIC-1605 provides an advanced solution to c onnect sata devices to usb with integrated cpu and embedded sram. to provide high perfor mance and cost effective solution, the inic- 1605 integrates usb-phy mass storage class bulk -only usb function, sata link/phy core and microprocessor into a single asic. the INIC-1605 provides the data transfer rate of up to 60 mb/sec connecting to a sata interface. 1.1 feature summary ? integrates usb2.0 phy ip core. ? data transfer rate of up to 60 mb/sec on usb side. ? integrated internal turbo 8051 up with 16kb embedded sram. ? program flash in-line (firmware download mechanis m, usb direct for mfg test, write .bta file. ? local bus interface to serial peri pheral interface (spi) flash only. ? support hid. ? up to 9 gpio pins. ? the option of using only one external crystal. ? provide software utilities for downloading the upgraded firmware code under usb. ? supports sata (bridged sata) hard disk drives, cd-rw devices, dvds, removable media devices ? usb 1.1 and usb 2.0 compliant. ? usb mass storage class bulk-only transport specification compliant. ? sata specification 1.0, sata ii and esat a compliant (hot plug is supported). ? supports sata ncq. ? supports 3gbps sata hdd connection to internal 1.5gbps sata ii phy. ? support ata/atapi device dma and pio mode. ? 4k bytes of data buffer for data transfer. ? one sata channel support. ? on-chip 3.3v to 1.8v regulator. ? 64 pin lqfp
INIC-1605 initio corporation 7 1.2 firmware/software support ? usb mass storage class bu lk-only transport support ? provide software utilities for downl oading the upgraded firmware code 1.3 devices support ? hard disk drives ? cd-rw devices ? dvds ? removable media devices
INIC-1605 initio corporation 8 2. INIC-1605 block diagram: figure1: usb to sata bridge block diagram disk data buffer (4 kbytes) & data flow control instruction sram 16 kbytes sata control block u p 8051 serial flash serial flash up to 64 kbytes usb phy usb core usb port sata transport layer sata link layer sata phy command buffers registers
INIC-1605 initio corporation 9 3. pin-out diagram: | | | | | | | | | | | | | | | | l p s s s v g v n n g v g n n g e o c d c 1 n 1 c c n 1 n c c n d r e k 8 d 8 d 8 d d s n t v18out --- 1 gnd --- 2 gnd --- 3 v18 --- 4 dm --- 5 dp --- 6 rext_usb --- 7 v33 --- 8 gnd --- 9 gnd --- 10 xin --- 11 xout --- 12 v18 --- 13 vbus --- 14 gnd --- 15 v33 --- 16 48 --- xtalo _ _ 47 --- xtali 46 --- gnd 45 --- rext_sata 44 --- v33 43 --- v18 42 --- v18 41 --- gnd 40 --- tx0p 39 --- tx0n 38 --- gnd 37 --- v18 36 --- gnd 35 --- rx0n 34 --- rx0p 33 --- v18 v g v v g p p p p p p p p t t t 3 n 1 3 n 1 1 1 1 1 3 3 3 e e e 3 d 8 3 d | | | | | | | | s s s 0 1 2 3 4 0 1 3 t t t 0 1 2 | | | | | | | | | | | | | | | | 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 INIC-1605
INIC-1605 initio corporation 10 4. pin signal descript ion: (64-pin package) 4.1 usb interface (analog pins except vbus) signal name pin number i/o driver type description dp 6 i/o usb high /full speed buffer (d+) high/full speed d+ signal dm 5 i/o usb high/full speed buffer (d-) high/full speed d- signal rext_usb 7 a power pll voltage reference. current source for 330 ohm(1%) resistor connected to avss vbus 14 i no internal pullup/down active high. indicates that vbus is present. xin 11 i a crystal oscillator input (12mhz) xout 12 o a crystal oscillator output (12mhz) 4.2 sata interface (analog pins) signal name pin number i/o driver type description tx0p (sata device) 40 o sata channel0 differential transmit positive signal line tx0n (sata device) 39 o sata channel0 differential transmit negative signal line rx0p (sata device) 34 i sata channel0 differential receive positive signal line rx0n (sata device) 35 i sata channel0 differential receive negative signal line xtalo 48 o crystal oscillator output rext_sata 45 i external reference resister (6.19 k ohm) 4.3 system interface signal name pin number i/o driver type description porst# 18 i internal pullup 80kohm power on reset. 4.4 miscellaneous interface signal name pin number i/o driver type description testmode[2:0] 49,50,51 i internal pulldown 80kohm test mode select 000: normal 001: reserved 010: testmux (internal testing) 011: usb phy test(internal testing) 100: sata phy test(internal testing) 101: scan test(atpg tests) 110: mbist test (internal testing) 111: por_from_pin_test(internal testing)
INIC-1605 initio corporation 11 4.5 serial flash interface signal name pin number i/o driver type description scen/ p1.7in/ gpio3 19 i/o internal pull down 80kohm 1. serial flash chip enable. 2. this pin also connects to up8051.p1.7in port. 3. this pin can also be configured as gpio3. 4. strap for usbpll_freq_sel. (0* : use crystal input 12mhz xin for usb pll.) (*default) (1 : use internal clock source for usb pll.) sd/ p1.6in/ gpio2 20 i/o internal pull down 80kohm 1. serial flash data input/output. 2. this pin also connects to up8051.p1.6in port. 3. this pin can also be configured as gpio2. sck/ p1.5in/ gpio1 21 i/o internal pullup 80kohm 1. serial flash clock. 2. this pin also connects to up8051.p1.5in port. 3. this pin can also be configured as gpio1 4.6 mvram/gpio interface signal name pin number i/o driver type description led 17 i/o internal pullup 80kohm led: sata activity indicator. p3.3/ int1# 52 i/o no internal pullup/down up8051 i/o port 3.3, can be used as gpio p3.1/ uart_txd 53 i/o internal pullup 80kohm up8051 i/o port 3.1, can be used as gpios p3.0/ uart_rxd 54 i/o internal pullup 80kohm up8051 i/o port 3.0, can be used as gpios p1.4 55 i/o internal pullup 80kohm up8051 i/o port 1.4, can be used as gpios p1.3 56 i/o internal pullup 80kohm up8051 i/o port 1.3, can be used as gpios p1.2/ refclksel_0 57 i/o internal pullup 80kohm up8051 i/o port 1.2, can be used as output gpio 1. the pullup/pulldown of pin58, pin57 will select the frequency of refclk: pin58 pin57 refclk pullup pulldown 100mhz pullup pullup 25mhz* pulldown pulldown 150mhz pulldown pullup 75mhz *: default selection is 25mhz p1.1/ refclksel_1 58 i/o internal pull up 80kohm note 1: p1.1 is used as strap pin only. p1.0 59 i/o internal pullup 80kohm up8051 i/o port 1.0, can be used as gpios
INIC-1605 initio corporation 12 4.7 power regulator pins signal name pin number i/o driver type description reg_vcc3 64 i total 1 pin reg_gnd 2 i total 1 pin reg_v18out 1 o total 1 pin 4.8 power/gnd signal name pin number i/o driver type description vcc3 16,61 2 pins (digital 3.3v) vcc18 22,62 2 pins (digital 1.8v) gnd 15,23,60,63 4 pins usb_vcc3a 8 1 pin:analog 3.3v (vd33p) usb_gnda 9 1 pin:analog gnd (vs33p) usb_vcc18a 13 1 pin:analog 1.8v (vdda) for usb pll usb_gnd18a 10 1 pin:analog gnd (vssa) for usb pll usb_vcc18 4 1 pin:digital 1.8v (vddu) usb_gnd18 3 1 pin:digital gnd (vssu) sata_vdda 24,28,33,37 4 pins (analog 1.8v) sata_vddp 42,43 2 pins (sata pll 1.8v) sata_vddo 44 1 pin (xtal pwr 3.3v) sata_gnda 27,29,32,36, 38,41,46 7 pins (analog gnd) 5. register address mapping: 5.1 general registers address read value write value 40a3h bufferrst bufferrst 40a6h testctl testctl 40ach led_spd led_spd 40adh miscen miscen 40afh miscctl miscctl 40b1h dmaflush dmaflush 40b2h usb channel set usb channel set 40b3h usb channel clear usb channel clear 40b4h dir/d2ben dir/d2ben 40b5h run run 40b6h sata config sata config 40b7h sata reset sata reset 40b8h satastatus na 40bdh spi_status spi-ctrl 40beh spi_rddata spi-wrdata 40bfh spi_command spi-command 40ddh spi_adr[7:0] spi_adr[7:0] 40deh spi_adr[15:8] spi_adr[15:8] 40dfh spi_adr[31:16] spi_adr[31:16]
INIC-1605 initio corporation 13 40f0h usbint_en usbint_en 40f2h sataint_en sataint_en 40f4h gpio_p_int_en gpio_p_int_en 40f5h gpio_n_int_en gpio_n_int_en 40f7h buffer clear buffer clear 40f8h gpioen gpioen 40f9h gpiodatain gpiodataout 40fah gpioouten gpioouten 40fbh usb clear usb clear 5.2 buffers address read value write value 4100h-413fh (64 bytes) control_in buffer can?t be written by cpu 4140h-417fh (64 bytes) cbw_in buffer cbw_in buffer 41c0h-41ffh (64 bytes) control_out buffer control_out buffer 4240h-427fh (64 bytes) csw_out buffer csw_out buffer 4280h-423fh (64 bytes) hid_out buffer hid_out buffer 5.3 usb control registers address read value write value 4500h-450fh usb control usb control 5.4 sata control registers address read value write value 4800h reserved reserved 4801h ata error shadow ata error shadow 4802h ata status shadow ata status shadow 4803h control flag control flag 4804h-480fh reserved reserved 4810h ata feature shadow ata feature shadow 4811h ata extended feature shadow ata extended feature shadow 4812h ata device/head shadow ata device/head shadow 4813h reserved reserved 4814h ata sector count shadow ata sector count shadow 4815h ata extended sector count shadow ata extended sector count shadow 4816h ata sector number shadow ata sector number shadow 4817h ata extended sector number shadow ata extended sector number shadow 4818h ata cylinder low shadow ata cylinder low shadow 4819h ata extended cylinder low shadow ata extended cylinder low shadow 481ah ata cylinder high shadow ata cylinder high shadow 481bh ata extended cylinder high shadow ata extended cylinder high shadow 481ch ata command shadow ata command shadow 481dh ata control shadow ata control shadow 4820h sata phy control [7:0] sata phy control [7:0] 4821h sata phy control [15:8] sata phy control [15:8] 4822h sata phy status [7:0] sata phy status [7:0]
INIC-1605 initio corporation 14 4823h sata phy status [15:8] sata phy status [15:8] 4830h-4833h sata status sata status 4834h-4837h sata error sata error 4838h-483bh sata control sata control 483ch-483fh sata active sata active 5.5 data buffer address read value write value 5000h-5fffh data buffer data buffer 5.6 usb registers address read value write value 6020h dev_status dev_status 6021h funct_adr funct_adr 6022h test_mode test_mode 6025h eptxlength[7:0] eptxlength[7:0] 6026h eptxlength[15:8] eptxlength[15:8] 6030h ep0_status ep0_ control (set) 6031h ep0_status ep0_ control (clear) 6032h ep0_status2 ep0_ control 2(set) 6033h ep0_status2 ep0_ control 2(clear) 6034h ep0txlength ep0txlength 6038-603f hdr0-7 - 6040h ep1_status ep1_ control (set) 6041h ep1_status ep1_ control (clear) 6050h ep2_status ep2_ control (set) 6051h ep2_status ep2_ control (clear) 6052h usb_rxlength[7:0] - 6060h ep3_status ep3_ control (set) 6061h ep3_status ep3_ control (clear) 6070h totalcnt0 totalcnt0 6071h totalcnt1 totalcnt1 6072h totalcnt2 totalcnt2 6073h totalcnt3 totalcnt3 6074h - loadtotalcnt 6080h gtotalcnt0 gtotalcnt0 6081h gtotalcnt1 gtotalcnt1 6082h gtotalcnt2 gtotalcnt2 6083h gtotalcnt3 gtotalcnt3 5.7 data space mapping mapping address type access type mapping block 0000h-3fffh data read/write internal sram (16kb) 4000h-47ffh data read/write internal register/buffers 4800h-48ffh data read/write sata registers 5000h-5fffh data read/write data buffer (4kb) 6000h-60ffh data read/write usb registers
INIC-1605 initio corporation 15 5.8 code space: internal sram: address read value write value 0-3fffh firmware code (16k bytes) (instruction fetch) n/a 6. programming guide: 6.1 usb direct access 8051?s code/data space (byte mode only) 1. host send read_chip_id packet through control channel to read chip-id, which is 0x29c5_1605 here. 2. host send hold_cpu packet through control channel to set hold_cpu bit. 3. host may send read_hold_cpu packet through control channel to read back hold_cpu bit. 4. host may send flash_write/flash_read/data_ write/data_read packet through control channel to write/read flash or data space. 6.2 hardware program/download procedure (byte mode only) INIC-1605 provides the mech anism for usb host to access the flash chip directly. host may program and read serial flash memory through default endpoint. flash write setup packet format is, offset field size value description 0 bmreqtype 1 0x40 vendor write 1 breq 1 flash write [7]: 0?flash memory [6]: 1?addr valid [5]: 1?data valid [4:0]: 5?h01?flash write 2 addr[7:0] 3 wvalue 2 addr[15:0] address to be written 4 data[7:0] 5 windex 2 opcode flash data 6 0x00 7 wlength 2 0x00 flash read setup packet format is, offset field size value data description 0 bmreqtype 1 0xc0 vendor read 1 breq 1 flash read [7]: 0?flash memory [6]: 1?addr valid [5]: 1?data valid [4:0]: 5?h02?flash read 2 addr[7:0] 3 wvalue 2 addr[15:0] address to be written 4 0x00 5 windex 2 opcode data from flash don?t care
INIC-1605 initio corporation 16 6 0x01 7 wlength 2 0x00 read_chip_id setup packet format is, offset field size value data description 0 bmreqtype 1 0xc0 vendor read 1 breq 1 0x03 2 0x00 3 wvalue 2 0x00 4 0x00 don?t care 5 windex 2 0x00 don?t care 6 0x04 7 wlength 2 0x00 chip-id 0x10, 0x16, 0xc9, 0x25 hold_cpu setup packet format is, offset field size value description 0 bmreqtype 1 0x40 vendor write 1 breq 1 0x04 hold_cpu 2 0x00 3 wvalue 2 0x00 don?t care 4 0x00 don?t care 5 windex 2 0x00 don?t care 6 0x00 don?t care 7 wlength 2 0x00 don?t care 6.3 spi serial flash programming guide: a1. serial peripheral interface (spi) serial flash operation: a1.1 hardware bootload: 1. after power on, hardware will automatically load 4 k by tes codes from spi serial flash (location 0000h ? 0fffh) i n internal memory(duplicates into two 4 k by tes area: location 0000-0fffh and 3000-3fffh). 2. after the hardware 4 k bytes bootload, firmware may exec ute this 4 k byte codes from memory location 0000h, a copy additional 12 k bytes code from serial flash into internal memory. please see the example in a1.2 for this copy sequences: a1.2 example for firmware to read codes from serial fl ash location 24?h00a000 and copy it into internal memory location 16?h0b00: 1. cpu writes register_40bf wi th 0x03 (command read) /* to prepare the command code */ 2. cpu writes register_40df with 0x00 (spi _adr[23:16]) /* to prepare the spi_addr */ 3. cpu writes register_40d e with 0xa0 (spi_adr[15:8]) 4. cpu writes register_40d d with 0x00 (spi_adr[7:0]) 5. cpu writes register_40bd with 0xe0 (spi_ctrl) /* to send out this read command to serial flash */ 6. cpu reads register_40be to trigger the read action. 7. cpu reads register_40bd, check if bit 0 becomes 1?b1. if yes, go to step 8, otherwise repeat step 7 8. cpu reads register_40be to get the content, and write it to internal memory location 16?0b00.
INIC-1605 initio corporation 17 a1.3 example for firmware to do sector_erase to serial flash location 24?h008xxx :( sector 8) 1. cpu writes register_40bf with 0x06 (command wren) /* to prepare the command code */ 2. cpu writes register_40bd with 0x80 (spi_ctrl) /* to send out this wren command to serial flash */ 3. cpu writes register_40bf with 0x20 /* command sector_erase */ 4. cpu writes register_40d f with 0x00 (spi_adr[23:16]) 5. cpu writes register_40de with 0x80 (spi_adr[15:8]) /* sector 8 */ 6. cpu writes register_40d d with 0x00 (spi_adr[7:0]) 7. cpu writes register_40be with dummy data (spi_data) 8. cpu writes register_40bd with 0xc0 (spi_ctrl) /* to send out this sector_erase command to serial flash */ 9. cpu writes register_40b f with 0x05 (command rdsr) 10. cpu writes register_40bd with 0xa0 (spi_ctrl) /* to send out this rdsr command to serial flash */ 11. cpu reads register_40b d, check if bit 0 becomes 1?b1. if yes, go to step 12, otherwise repeat step 11 12. cpu reads register_40be to get the status, check if bit 0 becomes 1?b0. if yes, go to step 13, otherwise go to step 9 13. cpu writes register_40bd with 0x00 (s pi_ctrl) /* turn off this control */ a1.4 example for firmware to write data to serial flash location 24?h008123: 1. cpu writes register_40bf with 0x06 (command wren) /* to prepare the command code */ 2. cpu writes register_40bd with 0x80 (spi_ctrl) /* to send out this wren command to serial flash */ 3. cpu writes register_40bf with 0x02 (command bytewr) 4. cpu writes register_40d f with 0x00 (spi_adr[23:16]) 5. cpu writes register_40d e with 0x81 (spi_adr[15:8]) 6. cpu writes register_40d d with 0x23 (spi_adr[7:0]) 7. cpu writes register_40b e with data (spi_data) 8. cpu writes register_40bd with 0xe0 (spi_ctrl) /* to send out this bytewr command to serial flash */ 9. cpu reads register_40bd, check if bit 1 becomes 1?b1. if yes, go to step 10, otherwise repeat step 9 10. cpu writes register_40bd with 0x00 (s pi_ctrl) /* turn off this control */ 7. register descriptions: 7.1 buffer reset register (0x40a3) field name rscu bit # reset description reserved r 7-5 3?b0 reserved. buffer1rst rw 4 1?b0 dma buffer 1 reset. this bit is used to reset dma bu ffer 1. this bit is self-cleared by hardware after set. reserved r 3-1 3?b0 reserved. buffer0rst rw 0 1?b0 dma buffer 0 reset. this bit is used to reset dma bu ffer 0. this bit is self-cleared by hardware after set. 7.2 test control register (0x40a6) field name rscu bit # reset description reserved r 7-6 2?b0 reserved. revid r 5-4 2?h0 revision id. these 2 bits are read only. testmuxsel rw 3-0 4?h0 test mux out put select. these 4 bits select specific internal signals to be routed to device?s outputs during te st mode. (internal testing purpose) 7.2.1 led_spd register (0x40ac) field name rscu bit # reset description reserved r 7-5 3?b0 reserved usb_wakeupen rw 4 1?b0 1: enable external interrupt wakeup usb when device is now in suspend state.
INIC-1605 initio corporation 18 led_spd [3 : 0] rw 3-0 4?h0 define led blink speed : 0000 : 1/32 sec. per blink 0001 : 2/32 sec. per blink up to ~ ~ 1111 : 16/32 sec. per blink 7.2.2 miscen register (0x40ad) field name rscu bit # reset description reserved r 7-6 2?b00 reserved reserved r 5 1?b0 reserved tl_wakeup rw 4 1?b0 control bit for sata block tl_slumber rw 3 1?b0 control bit for sata block tl_partial rw 2 1?b0 control bit for sata block sata_busy_sel rw 1 1?b0 0 : select sata_busy as sata device activity detection 1 : select (sata_busy or sata_drq ) as sata device activity detection reserved r 0 1?b0 reserved 7.3 miscctl register ( 0x40af): this 8-registers is in lclk domain (37.5 mhz) field name rscu bit # reset description sim_mode rw 7 1?b0 internal testing. do not set to 1. reserved r 6 reserved phyclk_ctl rw 5 1?b0 firmware set/clr this bit. if set, phy clock is free run. if clr, phy clock will stop when device goes to suspend mode. usb_enumeratio n rw 4 1?b1 1: enable usb enumeration. 0: disable usb enumeration. hw_rst_event rw 3 1?b1 this bit is set by hardware reset. software reset has no effect on this bit. firmware can clear this bit by writing a 0 to it. hiden rw 2 1?b0 1 : endpoint defined as: 8(in), 2(out), 1(int) 0 : endpoint defined as: 1(in), 2(out), 3(int) newmode rw 1 1?b0 1 : 1605 report residue same as totalcnt minus usb txed or rxed 0 : 1605 report residue same as totalcnt minus ata txed or rxed reserved r 0 1?b0 reserved 7.4 softrst register (0x40b0) field name rscu bit # reset description reserved r 7-1 7?b0 reserved. softrst w 0 1?b0 1: software reset (setting this bit will reset the data buffer related logic) 7.5 dma flush register (0x40b1) field name rscu bit # reset description reserved r 7-1 7?b0 reserved flush/abort rw 0 1?b0 when dma buffer is overrun, this bit is used by firmware to flush data out for outgoing data or abort the dma operation for incoming data. this bit is self-cleared by hardware. 7.6 usb channel set/clear regist er (0x40b2 set) (0x40b3 clear) field name rscu bit # reset description reserved r 7 7?b0 reserved cmdtx4run rwu 6 1?b0 the set register is set by software and cleared by hardware when transfer
INIC-1605 initio corporation 19 (for hid_out) is completed. when the clear register is set by software, the corresponding channel is cleared. cmdtx3run (for csw_out) rwu 5 1?b0 the set register is set by software and cleared by hardware when transfer is completed. when the clear register is set by software, the corresponding channel is cleared. reserved r 4 1?b0 reserved cmdtx1run (for control_out) rwu 3 1?b0 the set register is set by software and cleared by hardware when transfer is completed. when the clear register is set by software, the corresponding channel is cleared. reserved r 2-0 3?b0 reserved 7.7 dir/d2ben register (0x40b4) field name rscu bit # reset description dir rw 7 1?b0 indicates the di rection of the data transfer: 0: data write into sata device. 1: data output from sata device. proper dir bit must be programmed before writing ata command d2ben rw 6 1?b 0 data to buffer mode enable. the two sata channels can be configured to transfer data to and fr om the buffer memory without a host connection. reserved r 5-0 6?b 0 reserved 7.8 run register (0x40b5) field name rscu bit # reset description phaseerror rws 7 1?b 0 phase error status. set by hardware. reserved r 6-1 6?b 0 reserved run rw 0 1?b 0 write 1: start the data transfer; the hardware will clear this bit when the transfer is completed. firmware also can write 0 to clear this bit. d2ben (register 0x40b4 bit 6) and run (register 0x40b5 bit 0) work together to start di fferent data transfer: d2ben run 0 0 : idle 0 1 : start transfer between usb and sata device according to the dir bit ( register 0x40b4 bit 7 ) . 1 0 : idle 1 1 : start transfer between dma buffer and sata device according to the dir bit ( register 0x40b4 bit 7 ) 7.9 sata config register (0x40b6) field name rscu bit # reset description hwflushen rw 7 1?b1 when set to 1: automatic hardware flush is enabled. phaseerren rw 6 1?b1 when set to 1: an phaseerr event will report phaseerr to
INIC-1605 initio corporation 20 register 0x40b5 bit 7. led_idle_high rw 5 1?b0 0: sata idle will drive led pin low 1: sata idle will drive led pin high led_busy_sel rw 4 1?b0 0 : sata busy will blink led 1 : sata busy will drive led on reserved r 3-0 4?b0 reserved 7.10 sata reset register (0x40b7) field name rscu bit # reset description ataphyrst rw 7 1?b 0 sata channels hard reset to phy layer, auto-clear by hardware reserved r 6-5 2?b0 reserved. ataupprst rw 4 1?b 0 sata channel 0 reset to link/transport/application layer reserved r 3-1 3?b0 reserved. atach0int r 0 1?b0 sata channel 0 interrupt signal. 7.11 spi ctrl/status register (0x40bd) (for spi-serial flash only) field name rscu bit # reset description startcmd w 7 1?b0 1: cpu write 1 to start the serial flash?s command phase spi_adrvalid w 6 1?b0 1: validate the address field in the spi command spi_datavalid w 5 1?b0 1: validate the data field in the spi command startwrsr w 4 1?b0 1: cpu write 1 to start the serial flash?s write_status_register action reserved r 3-2 2?b0 spi_wrdone r 1 1?b0 read only: cpu has send out the serial write command to serial flash. cpu may start sending out the read_status_command (rdsr) to serial flash to check the busy bit. when busy bit is 0, it means serial flash has finished the write operation. spi_rddatardy r 0 1?b0 read only: cpu has send out the serial read command to serial flash. 7.12 spi_data register (0x40 be) (for spi-serial flash only) field name rscu bit # reset description spi_data rw 7-0 8?h0 this is the data port for cpu to access aerial flash a: to write to serial flash: cpu writes to this port: cpu writes a 8-bit data to serial flash. b: to read from serial flash: cpu reads this port: cpu does 1 st read: cpu activates the read action to fetch data from serial flash. cpu poll spi_rddatardy (register bd bit 0) until it is 1 cpu does 2nd read: to actually get the data.
INIC-1605 initio corporation 21 7.13 spi_cmd register (0x40bf) (for spi-serial flash only) field name rscu bit # reset description spi_cmd rw 7-0 8?h0 cpu writes the to-be executed spi_command code in this register. for example: spi_read has a command code: 03h 7.14 spi_adr[7:0] register (0x40 dd) (for spi-serial flash only) field name rscu bit # reset description spi_adr[7:0] rw 7-0 8?h0 cpu writes the to-be executed spi_adr[7:0] code in this register. 7.15 spi_adr[15:8] register (0x40d e) (for spi-serial flash only) field name rscu bit # reset description spi_adr[15:8] rw 7-0 8?h0 cpu writes the to-be executed spi_adr[15:8] code in this register. 7.16 spi_adr[23:16] register (0x40df) (for spi-serial flash only) field name rscu bit # reset description spi_adr[23:16] rw 7-0 8?h0 cpu writes the to-be executed spi_adr[23:16] code in this register. 7.17 usb_int_enable register (0x40f0) field name rscu bit # reset description usb_busrst_int_ en rw 7 1?b0 1: enable usb_busrst to trigger sysint. to check if this int has occurred, please read register 6030 bit 6. usb_bulkonlyrst_ int_en rw 6 1?b0 1: enable usb_bulkonlyrst to trigger sysint. to check if this int has occurred, please read register 6030 bit 5. usb_ep0req_int _en rw 5 1?b0 1: enable usb_ ep0req to trigger sysint. to check if this int has occurred, please read register 6032 bit 0. usb_cbw_int_e n rw 4 1?b0 1: enable usb_cbw to trigger sysint. to check if this int has occurred, please read register 6050 bit 1. usb_wakeup_int_ en rw 3 1?b0 1: enable usb_wakeup to trigger sysint. to check if this int has occurred, please read register 6020 bit 3. (value 0 means wakeup) usb_suspendint_ en rw 2 1?b0 1: enable usb_suspend to trigger sysint. to check if this int has occurred, please read register 6020 bit 3. (value 1 means suspend) vbus_p__int_e n rw 1 1?b0 1: enable positive of vbus to trigger sysint. to check if this int has occurred, please read register 40af
INIC-1605 initio corporation 22 bit 6. (value 1 means vbus is high) vbus_n__int_e n rw 0 1?b0 1: enable negative of vbus to trigger sysint. to check if this int has occurred, please read register 40af bit 6. (value 1 means vbus is high) 7.18 sata_int_enable register (0x40f2) field name rscu bit # reset description reserved r 7-3 5?b0 reserved sata_dev_int_ en rw 2 1?b0 1: enable sata_dev_int to trigger sysint. to check if this int has occurred, please read register 40b7 bit 0. sata_phyrdy_p_ int_en rw 1 1?b0 1: enable positive of sata_p hyrdy to trigger sysint. to check if this int has occurred, please read register 4820 bit 0. sata_phyrdy_n _int_en rw 0 1?b0 1: enable negitive of sata_phyrdy to trigger sysint. to check if this int has occurred, please read register 4820 bit 0. 7.19 sata_busy_int register (0x40f3) field name rscu bit # reset description reserved r 7-4 4?b0 reserved reserved r 3-0 4?b0 reserved 7.20 gpio_p_int_enable re gister (0x40f4) field name rscu bit # reset description reserved rw 7-4 4?b0 reserved gpio3_p_int_en rw 3 1?b0 1: enable gpio3 high level to trigger sysint. gpio2_p_int_en rw 2 1?b0 1: enable gpio2 high level to trigger sysint. gpio1_p_int_en rw 1 1?b0 1: enable gpio1 high level to trigger sysint. gpio0_p_int_en rw 0 1?b0 1: enable gpio0 high level to trigger sysint. 7.21 gpio_n_int_enable re gister (0x40f5) field name rscu bit # reset description reserved r 7-4 4?b0 reserved gpio3_n_int_en rw 3 1?b0 1: enable gpio3 low level to trigger sysint. gpio2_n_int_en rw 2 1?b0 1: enable gpio2 low level to trigger sysint. gpio1_n_int_en rw 1 1?b0 1: enable gpio1 low level to trigger sysint. gpio0_n_int_en rw 0 1?b0 1: enable gpio0 low level to trigger sysint. 7.22 buffer clear register (0x40f7) field name rscu bit # reset description
INIC-1605 initio corporation 23 reserved r 7-1 4?b0 reserved clear buffer rw 0 1?b0 1: clear data buffer and state machine. 7.23 gpio_enable register (0x40f8) field name rscu bit # reset description reserved rw 7-4 4?b0 reserved gpio3_en rw 3 1?b0 1: use scen pin as gpio3 gpio2 _en rw 2 1?b0 1: use sd pin as gpio2 gpio1 _en rw 1 1?b0 1: use sck pin as gpio1 gpio0 _en rw 0 1?b0 1: use led pin as gpio0 7.24 gpio_data register (0x40f9) field name rscu bit # reset description reserved rw 7-4 4?b0 reserved gpio3_data rw 3 1?b0 read: read the value of sc en pin (i.e. gpio3_datain) write: write the value to gpio 3_dataout (i.e. scen pin) gpio2 _data rw 2 1?b0 read: read the value of sd pin (i.e. gpio2_datain) write: write the value to gp io2_dataout (i.e. sd pin) gpio1 _data rw 1 1?b0 read: read the value of sck pin (i.e. gpio1_datain) write: write the value to gpio1_dataout (i.e. sck pin) gpio0 _data rw 0 1?b0 read: read the value of led pin (i.e. gpio0_datain) write: write the value to gpio0_dataout (i.e. led pin) 7.25 gpio_output_enable register (0x40fa) field name rscu bit # reset description reserved rw 7-4 4?b0 reserved gpio3_output_en rw 3 1?b0 0: select gpio3 to input mode 1: select gpio3 to output mode gpio2_output_en rw 2 1?b0 0: select gpio2 to input mode 1: select gpio2 to output mode gpio1_output_en rw 1 1?b0 0: select gpio1 to input mode 1: select gpio1 to output mode gpio0_output_en rw 0 1?b0 0: select gpio0 to input mode 1: select gpio0 to output mode 7.26 usb clear register (0x40fb) field name rscu bit # reset description reserved r 7-1 4?b0 reserved clear usb rw 0 1?b0 1: clear usb traffic problem. (when usb traffic encounter problem)
INIC-1605 initio corporation 24 7.27 buffer address map address description 4100-413fh control_in buffer, 64 bytes 4140-417fh cbw_in buffer, 64 bytes 41c0-41ffh control_out buffer, 64 bytes 4240-426fh csw_out buffer, 48 bytes 4280-42afh hid_out buffer, 48 bytes 7.28 usb control address description 4500-450fh usb control 450eh bit 7-0: datalength[7:0] 450fh bit 7-0: datalength[15:8] 8. sata channel registers (0x4800-0x483f): 8.1 command parameter blocks (cpb) structure definition 31 24 23 16 15 08 07 00 control flag ata status ata error reserved 4800h reserved 4804h reserved 4808h reserved 480ch reserved ata device/head ata ex. feature ata feature 4810h ata ex. sector number ata sector number ata ex. sector count ata sector count 4814h ata ex. cylinder high ata cylinder high ata ex. cylinder low ata cylinder low 4818h reserved reserved ata control ata command 481ch 8.1.1. ata error shadow offset: 4801h when the host programs the cpb, this byte of data is ignored. at the end of a command, the idma engine will update the content of this register to reflect the c ontent of the ata error register after status update. bit name definition 07-00 0 ataerr ata error register content. 8.1.2. ata status shadow offset: 4802h when the host programs the cpb, this byte of data is ignored. at the end of a command, the idma engine will update the content of this register to reflect the c ontent of the ata status register after status update. bit name definition 07-00 0 atastat ata status register content.
INIC-1605 initio corporation 25 8.1.3. control flags offset: 4803h bit name definition 07-04 5?h0 rsvd reserved. 03 0 ppkt packet command. when set, indicating the current command is an atapi packet command. after sending the register fis to the device, hardware will automatically fetch the cdb from cmdreceive buffer and send to device through pio. 01-00 2?h0 cdbs packet command cdb structure size in bytes. 00: 8 bytes 01: 12 bytes 10: 16 bytes 11: reserved 8.1.4. reserved offset: 4804-4807h 8.1.5. ata feature shadow offset: 4810h bit name definition 07-00 0 atafeat ata feature register content. 8.1.6. ata extended feature shadow offset: 4811h bit name definition 07-00 0 ataexfeat ata extended feature register content. 8.1.7. ata device/head shadow offset: 4812h bit name definition 07-00 0 atadevhd ata device/head register content. 8.1.8. ata sector count shadow offset: 4814h bit name definition 07-00 0 ataseccnt ata sector count register content. 8.1.9. ata extended sector count shadow offset: 4815h bit name definition 07-00 0 ataexseccnt ata extended sector count register content.
INIC-1605 initio corporation 26 8.1.10. ata sector number shadow offset: 4816h bit name definition 07-00 0 atasecnum ata sector number register content. 8.1.11. ata extended sector number shadow offset: 4817h bit name definition 07-00 0 ataexsecnum ata extended s ector number register content. 8.1.12. ata cylinder low shadow offset: 4818h bit name definition 07-00 0 atacyllo ata cylinder low register content. 8.1.13. ata extended cylinder low shadow offset: 4819h bit name definition 07-00 0 ataexcyllo ata extended cylinder low register content. 8.1.14. ata cylinder high shadow offset: 481ah bit name definition 07-00 0 atacylhi ata cylinder high register content. 8.1.15. ata extended cylinder high shadow offset: 481bh bit name definition 07-00 0 ataexcylhi ata extended cylinder high register content. 8.1.16. ata command shadow offset: 481ch bit name definition 07-00 0 atacmd ata command register content. 8.1.17. ata control shadow offset: 481dh bit name definition 07-00 0 atactl ata control register content.
INIC-1605 initio corporation 27 8.2 sata phy low cont rol register (4820h) field name rscu bit # reset description pw_dn_txpll rw 7 0 power down for tx-pll drv_level_1 rw 6 0 1: select 700mv output driver for channel 1 0: select 500mv output driver for channel 1 pw_dn_rxpll rw 5 0 power down for rx-pll slct5_15 rw 4 0 over sampling method select 1: select 15 bit processing window 0: select 5 bit processing window bypass_calib rw 3 1 disable calibration process during oob farafleb rw 2 0 place phy in far-end analog loopback mode nearafleb rw 1 0 place phy in near-end analog loopback mode fphyrdy rw 0 0 force phy ready 8.3 sata phy highcontrol register (4821h) field name rscu bit # reset description reserved rw 15-12 4?b0 000 pw_dn_ch0 rw 11 0 power down for phy channel 0, bias circuit and calibration circuits drv_level_0 rw 10 0 1: select 700mv output driver for channel 0 0: select 500mv output driver for channel 0 pw_dn_ch1 rw 9 0 power down for channel 1 (high speed io only) tx_pl_err_rst rw 8 0 tx phase error reset 8.4 sata phy low status register (4822h) field name rscu bit # reset description oob_status_1 r 7 0 oob_status_0 r 6 0 tx_pl_err_lvl0 r 5 0 rx_or_err_lvl0 r 4 0 squelch r 3 0 squelch_err r 2 0 slumber_out r 1 0 partial_out r 0 0 8.5 sata phy high status register (4823h) field name rscu bit # reset description phystatus[15:10] rw 15-10 6?h0 phy status[15:10] oob_status_3 r 9 oob_status_2 r 8 when 4bits oob_staus_3~0 is 4?b1010, it means phy is ready, all other states mean not ready
INIC-1605 initio corporation 28 8.6 sata status register (4830h-4833h) field name rscu bit # reset description sstatus r 31-0 32?b 0 sata status 8.7 sata error register (4834h-4837h) field name rscu bit # reset description serror r 31-0 32?b 0 sata error 8.8 sata control regi ster (4838h-483bh) field name rscu bit # reset description scontrol rw 31-0 32?b 0 sata control 9. data buffer: address read value write value 5000h-5fffh data buffer data buffer 10. usb registers: 10.1 device status (dev_status[7:0], 0x6020) field name rscu bit # reset description vbus r 7 1?b0 read: usb?s vbus status test_mode rsu 6 1?b0 set when set_feature (test_mode). attach ru 5 1?b1 hardware reset default state. clear if detect vbus valid. then set power bit powered ru 4 1?b0 set if vbus=1 & previ ous state is attach. or, power interruption. suspend ru 3 1?b0 after bus idle for sometime, ha rdware set this bit. when resume detected, hardware reset this bit and return to previous state default ru 2 1?b0 after bus rese t, hardware set this bit. addressed rscu 1 1?b0 set_addr ess or set_configuration(0) configured rscu 0 1?b0 set_configuration 10.2 function address (funct_adr[7:0], 0x6021) field name rscu bit # reset description rsvd ru 7 1?b0 reserved adr ru 6:0 7?b0 set_address 10.3 test mode (test_mode[7:0], 0x6022) field name rscu bit # reset description rsvd ru 7:4 4?b0 reserved
INIC-1605 initio corporation 29 test_mode rwu 3:0 4?b0 test mode se lectors(table 9-7, usb2.0 spec) 4?h1: test_j 4?h2: test_k 4?h4: test_se0_nak 4?h8: test_packet others: rsvd 10.4 end point tx data length low bytes (ep_txlength[7:0], 0x6025) field name rscu bit # reset description ep_txlength rwu 7:0 8?b0 for ep1 (bulk_in): for ata-command-no-dma-involved, this field indicates how many bytes sent back to host. maximum 512-bytes 10.5 end point tx data length high bytes (ep_txlength[15:8], 0x6026) field name rscu bit # reset description rsvd r 7:2 6?b0 reserved ep_txlength rwu 1:0 2?b0 high bytes 10.6 end point 0 status/control (ep0_sta tus [7:0], 0x6030: set, 0x6031: clear) field name rscu bit # reset description suspend_gnt rsc 7 1?b0 suspend-request granted usb_busrst rcu 6 1?b0 set by hardware after an usb bus reset detected . clear by firmware. bulk_only_rst rcu 5 1?b0 set by hardware, read an d cleared by firmware after firmware responds bulk-only-reset command done. ep0_line_st ru 4:3 2?b0 line states ep0_speed ru 2 1?b0 1?hs, 0--fs remote_wakeup rscu 1 1?b0 set/clr by firmware. remote wakeup request. halt rscu 0 1?b0 1-ep0 halt. function stall. device reset is require to clear this bit 10.7 end point 0 status/control2 (ep0_status2 [7:0], 0x6032: set, 0x6033: clear, bulk-in) field name rscu bit # reset description fw_rdy rsc 7 1?b0 0: default value as no firmwa re installed. hardware response all control packets for firmware download in most cases. 1: firmware controls some setup packet response. rsvd r 6:4 3?b0 reserved ep0_statrun rsu 3 1?b0 set by firmware if devi ce ready to go to control status stage. ep0_out rcu 2 1?b0 set by hardware if a control co mmand-data is received. clear by firmware after processing. ep0_run rsu 1 1?b0 set by firmware. when firmware se t this bit, the data will be transferred from data buffer to usb. how many bytes transferred is based on the data transfer length in the ep_txlength( 0x25, 0x26) ep0_setup rcu 0 1?b0 set by hardware if a contro l command is received. clear by firmware after processing.
INIC-1605 initio corporation 30 10.8 end point tx data length low bytes (ep0txlength [7:0], 0x6034) field name rscu bit # reset description rsvd r 7 1?b0 reserved ep0txlength rwu 6:0 7?b0 for ep0 (control): this fi eld is filled by firmware . when firmware taking control setup packet response, firmware write this fiel d to inform hardware the data length to be send back to host. maximum 64-bytes. 10.9 setup packet (hdr0?hdr7 [7:0], 0x6038?0x603f) field name rscu bit # reset description hdr ru 7:0 8?bx 8 bytes setup packet. 10.10 end point 1 status/control (ep1_status [7 :0], 0x6040: set, 0x6041: clear, bulk-in) field name rscu bit # reset description gtotalcnteq 0 r 7 0 1? ata global total counter equal 0 0--- ata global total counter not equal 0 totalcnteq0 r 6 0 1? ata total counter equal 0 0--- ata total counter not equal 0 rsvd r 5:4 2?b0 reserved csw_run rscu 3 1?b0 set by firmware when firmware ready to send csw. clear by hardware after csw is sent successfully. rsvd r 2 1?b0 reserved ep1_run rscu 1 1?b0 set by firmware. when firmware se t this bit, the data will be transferred from data buffer to usb. how many bytes transferred is based on the data transfer length in the ep_txlength( 0x25, 0x26) halt rscu 0 1?b0 1-ep1 halt. 10.11 end point 2 status/control (ep2_status [7:0], 0x6050: set, 0x6051 clear, bulk-out) field name rscu bit # reset description fs_en rw 7 1?b0 force device to full speed only mode rsvd r 6:3 4?b0 reserved ep2_rx rcu 2 1?b0 set by hardware after the bulk out packet received. th e number of total data length received will be shown in usb_rxl ength register. this bit is used by firmware to monitor the data transfer between usb and internal data buffer. this bit is cleared by firmware or automatically cleared by hardware after the next cbw received or sg0r un bit set by firmware. ep2_cbw rcu 1 1?b0 set by hardware if a valid cbw received. clear after processing by firmware. halt rscu 0 1?b0 1-ep2 halt. 10.12 usb_rxlength (usb_rxlength[7:0], 0x6052, bulk-out) field name rscu bit # reset description rxlength ru 7:0 8?b0 the low byte of data length r eceived. this register is used to show how many date received from usb to internal data buffer.
INIC-1605 initio corporation 31 10.13 end point 3 status/control (ep3_status [7 :0], 0x6060: set, 0x6061: clear, intr-in) field name rscu bit # reset description rsvd r 7:3 5?b0 reserved ep3_run rsu 2 1?b0 1?packet ready. cleared by hardware after tx completed rsvd r 1 1?b0 reserved halt rscu 0 1?b0 1-ep3 halt. 10.14 end point tx data length low bytes (ep3txlength [7:0], 0x6062) field name rscu bit # reset description rsvd r 7 1?b0 reserved ep3txlength rwu 7:0 7?b0 for ep3 (int_in): this field is filled by firmware. firmware writes this field to inform hardware the data length to be sent back to host. maximum 64- bytes. 10.15 total count0 (totalcnt[7:0], 0x6070 totalcnt0) field name rscu bit # reset description totalcnt0 rwu 7-0 8?b0 totalcnt[7:0] 10.16 total count1 (totalcnt[15:8], 0x6071 totalcnt1) field name rscu bit # reset description totalcnt1 rwu 7-0 8?b0 totalcnt[15:8] 10.17 total count2 (totalcnt[23:16], 0x6072 totalcnt2) field name rscu bit # reset description totalcnt2 rwu 7-0 8?b0 totalcnt[23:16] 10.18 total count3 (totalcnt[31:24], 0x6073 totalcnt3) field name rscu bit # reset description totalcnt3 rwu 7-0 8?b0 totalcnt[31:24] 10.19 load total count (load totalcnt, 0x6074) field name rscu bit # reset description reserved r 7-1 7?b0 reserved loadtotalcnt w 0 1?b0 write an 1 to this bit will re-load the value from register 0x73-0x70?s totalcnt[31:0] to internal counter.
INIC-1605 initio corporation 32 10.20 global total count0 (gtotalcnt[7:0], 0x6080 gtotalcnt0) field name rscu bit # reset description gtotalcnt0 rwu 7-0 8?b0 gtotalcnt[7:0] 10.21 global total count1 (gtotalcnt[15:8], 0x6081 gtotalcnt1) field name rscu bit # reset description gtotalcnt1 rwu 7-0 8?b0 gtotalcnt[15:8] 10.22 global total count2 (gtotalcnt[23:16], 0x6082 gtotalcnt2) field name rscu bit # reset description gtotalcnt2 rwu 7-0 8?b0 gtotalcnt[23:16] 10.23 global total count3 (gtotalcnt[31:24], 0x6083 gtotalcnt3) field name rscu bit # reset description gtotalcnt3 rwu 7-0 8?b0 gtotalcnt[31:24] 11. electrical information: 11.1 absolute maximum ratings symbol parameter min max units vcc power supply -0.3 3.6 v vin input voltage -0.3 vcc+0.3 v vout output voltage -0.3 vcc+0.3 v tstg storage temperature -55 150 c 11.2 recommended operating conditions symbol parameter min typ max units vcc power supply 3.0 3.3 3.6 v vin input voltage 0 - vcc v commercial junction operating temperature 0 25 115 c tj industrial junction operation temperature -40 25 125 c 11.3 general dc characteristics symbol parameter min typ max units iil input leakage current -1 1 a ioz tristate leakage current -1 1 a cin input capacitance 2.8 pf cout output capacitance 2.7 4.9 pf cbid bi-directional buffer capacitance 2.7 4.9 pf
INIC-1605 initio corporation 33 11.4 dc electrical characterist ics for 3.3v operation (under vcc=3.0-3.6v, tj=0-115c) symbol parameter conditions min typ max units vil input low voltage cmos -0.3 0.8 v vih input high voltage cmos 2.0 5.5 v vol output low voltage ioh-2-24ma 0.4 v voh output high voltage ioh=2-24ma 2.4 v ri input pullup/pulldown resistance vil=0/vih=vcc 75 k icc operating supply current vcc=3.3v 150 ma 12. packaging specification

(q2) (q3) q q1
q q3 q2 q1

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